A power supply circuit converts input voltage to output voltage being different from the input voltage. The power supply circuit that performs such a voltage conversion is also referred to as a DC-DC converter, and is widely used for a mobile phone and a mobile terminal that includes a low power LSI.
FIG. 1 illustrates a block diagram of a general wireless transmission terminal. FIG. 1 illustrates an example of the transmission terminal in which a signal from a baseband processor is converted to a signal of an RF (Radio Frequency) band by an RF transmitter, and the signal is amplified by a power amplifier (PA) and transmitted from an antenna. The DC-DC converter supplies each circuits with power desired for each of the circuits.
FIG. 2 illustrates a circuit diagram of a common DC-DC converter. The DC-DC converter includes a first switch M1, a second switch M2, an output inductor L, and a control unit 80. The first switch M1 and the second switch M2 are connected in series between an input voltage terminal IN for receiving input voltage Vin and a reference terminal for supplying reference power supply voltage (for example, ground) that is lower than the input voltage. The output inductor L, such as a coil, is provided between a connection node (or connection point) LX of the first and second switches and an output terminal OUT for supplying output voltage Vout. The control unit 80 alternately switches, with a certain switching cycle, between the first switch M1 and the second switch M2 depending on the difference between a target voltage and the output voltage Vout. A smoothing capacitor C is connected to the output terminal OUT to constitute a smoothing circuit for smoothing the output voltage Vout.
The first switch M1, which is a high-side transistor, is a P-channel MOS transistor and operated by the control unit 80 with a gate drive signal VC that is generated by the control unit. The second switch M2, which is a low-side transistor, is an N-channel MOS transistor and operated by the control unit 80 with a gate drive signal VC that is generated by the control unit.
The gate of the first switch M1 and the gate of the second switch M2 are connected to a buffer B3 and a buffer B4, respectively, that perform level conversion of the gate drive signal VC generated by the control unit 80.
A resistor R that is connected to the output terminal OUT represents a load circuit of an LSI, etc. that receives voltage supplied by the DC-DC converter.
In this kind of DC-DC converter, increase in loss at a light load state, that is, reduction of efficiency is often seen as a problem.
FIG. 3 shows a timing chart describing a problem at a light load state or a no-load state. The signal VC that controls the first switch M1 and the second switch M2 is output from the control unit 80, and the first switch M1 is turned on and the second switch M2 is turned off when the signal VC is in a high level.
At this time, when a voltage of the input voltage terminal IN is represented by VIN, current that flows through the output inductor L is charged to the smoothing capacitor C in accordance with a slope of (VIN−VOUT)/L illustrated in FIG. 3, and an output potential VOUT is gradually increased. Next, the signal VC is set to a low level by the control unit 80, the first switch M1 is turned off, and the second switch M2 is turned on. At this time, current that flows through the output inductor L is charged to the smoothing capacitor C in accordance with a slope of (−VOUT)/L illustrated in FIG. 3 while gradually reducing the current value, and then the output potential VOUT is gradually reduced.
The control unit 80 switches between the first switch M1 and the second switch M2, depending on the difference between the output voltage Vout and the target voltage. In the case illustrated in FIG. 3, a ripple component is suppressed to the region between potentials VH and VL. By repeating the switching operation, the output potential VOUT has a repetitive waveform between potentials VH and VL, so that a DC-power supply as a fixed potential may be obtained. The value of VOUT depends on a rate (duty) of time periods during which the first switch M1 and the second switch M2 are turned on and off. For example, when a time during which the first switch M1 is turned on becomes longer, that is, when the duty is higher, the potential of VOUT becomes a high DC potential. When the duty is 50% as illustrated in FIG. 3, “VOUT=VIN/2” is satisfied.
On the other hand, a potential VLX of the node of connection point LX between the first switch M1 and the second switch M2 is reduced to a potential lower than the GND level by turning on the second switch M2. This is why, even after the second switch M2 is turned on, the output inductor L works to maintain the electric current IL which flows through the output inductor L while the first switch M1 is turned on. Thus, the potential VLX is reduced to a GND level or less, and the current IL flows from the GND to the VOUT.
When the first switch M1 is turned on, the opposite phenomenon occurs such that the node potential VLX is increased to a positive potential and the current IL is maintained even after the switching. Therefore, as illustrated in FIG. 3, the node potential VLX has a waveform that is obtained by inverting positive and negative potentials.
Here, a case is assumed in which load current of the DC-DC converter is significantly small, for example, the wireless transmission terminal that is illustrated in FIG. 1 is in a power-down mode that is a state in which a signal is not transmitted such as a state in which a desired current amount becomes small. Generally, this state is referred as a light load. In the light load state, as illustrated by the broken line of FIG. 3, the current IL that flows through the output inductor L becomes markedly small. In this state, the slope of the current IL is not changed because the slope is uniquely determined by the output inductor L and the potential difference between VIN and VOUT, so that there is a time period during which the current IL that flows through the output inductor L becomes negative. In the time period, the current IL flows from the output terminal OUT side of the output inductor L to the connection node LX side, charges are discharged from the smoothing capacitor C. The node potential VLX becomes as illustrated by the broken line, and charges that have been charged to the smoothing capacitor C are discharged to the GND side through the second switch M2 without supplying the charges to the load circuit by turning the node potential VLX to positive voltage. This causes a problem of “reduction of efficiency in the light load state”.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2009-124844,    [Document 2] Japanese Laid-open Patent Publication No. 2010-273446, and    [Document 3] Japanese Laid-open Patent Publication No. 2011-72101.